1. Field of the Invention
The present invention relates to semiconductor power components, that is, components capable of switching high currents and/or withstanding high voltages.
2. Discussion of the Related Art
Conventionally, power and/or high voltage components used to be discrete components. To ensure the lateral insulation of the components and improve their breakdown voltage, the component periphery is formed of an insulating wall formed by deep diffusion of dopant atoms from the upper and lower surfaces of a silicon wafer, the cutting being formed in the middle of this insulating wall.
With the development of technology, several power components and especially several vertical components can now be manufactured in the same chip. Examples of such structures are described in patent application EP-A-0721218 of the applicant (inventor R. Pezzani) which will be considered herein as known. This application is incorporated herein by reference. In EP-A-0721218, as in all descriptions of components formed in wells separated by insulating walls, it is assumed that each of the components formed in a well surrounded with an insulating wall is properly insulated from adjacent components which do not influence one another.
The applicant has noted in some structures including components formed in distinct wells separated by insulating walls that the flowing of a high current through a component could have an effect upon an adjacent component. Accordingly, in unpublished French patent application No. 97/06822 filed on May 28, 1997 and incorporated herein by reference (inventors F. Duclos and F. Rami), the applicant has analyzed the problem, distinguished xe2x80x9cstaticxe2x80x9d insulation from xe2x80x9cdynamicxe2x80x9d insulation, and provided a modification of the insulating wall structure to solve the problem.
More specifically, the applicant has provided an insulating wall structure which has a doping level greater than 1016 atoms/cm3 in its median part, at the meeting point of the deep diffusions formed from the upper and lower surfaces, and has also provided that, preferably, the median portion of the insulating wall has a lateral extension greater than the half-thickness of the wafer in which the deep diffusions are formed.
This prior solution implies, for a wafer of given thickness, to increase the duration of the diffusion annealing during the formation of the insulating walls and/or to increase the width of the insulating walls.
In the case where particularly intense currents have to flow through some wells, insulating walls having widths greater than the thickness of the semiconductive wafer have to be provided, to properly insulate the neighboring wells, which means that, in top view, the silicon surface occupied by the insulating walls becomes very large.
The present invention aims at providing an insulating wall structure such that the leakage currents between adjacent wells are particularly small.
Another object of the present invention is to provide an insulating wall structure such that the surface occupied by the insulating wall is reduced for intense currents.
To achieve these and other objects, the present invention provides an insulating wall of the second conductivity type intended for separating elementary components formed in different wells of a semiconductive wafer of a first conductivity type, a component located in one at least of the wells being likely to operate with a high current density. The insulating wall includes at least two elementary insulating walls separated by a portion of the wafer material and, in operation, this portion is connected to a reference potential.
According to an embodiment of the present invention, the width of the openings from which are formed the dopant diffusions into the upper and lower substrate surfaces is smaller than the half-thickness of the wafer.
This insulating wall applies to separating two wells containing vertical triacs.
This insulating wall applies to separating two wells, one at least of which includes a diode, a thyristor, or a vertical triac.
This insulating wall applies to a structure in which the various components are of vertical type and the semiconductive wafer includes a single rear surface metallization.
The foregoing objects, features and advantages of the present invention, will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings.